The present invention relates to a nonvolatile semiconductor memory device including a floating gate. More particularly, the invention relates to a nonvolatile memory device which can be manufactured by simple manufacturing steps.
As one type of a nonvolatile memory device, a stacked-gate nonvolatile memory device including a floating gate electrode provided on a semiconductor layer through an insulating layer, a control gate electrode provided on the floating gate electrode through an insulating layer, and a source region and a drain region provided in the semiconductor layer can be given. In such a stacked-gate nonvolatile memory device, writing and erasing are performed by applying a predetermined voltage to the control gate electrode and the drain region to cause injection or discharging of electrons into or from the floating gate electrode.
However, since the stacked-gate nonvolatile memory device involves gate electrode formation steps twice, the number of steps is increased. Moreover, since it is necessary to form a thin insulating layer on the floating gate electrode, the manufacturing steps become complicated.
As a nonvolatile memory device which can be manufactured at low cost using simple manufacturing steps in comparison with the stacked-gate nonvolatile memory device, a nonvolatile memory device disclosed in Japanese Patent Application Laid-open No. 63-166274 has been proposed. In the nonvolatile memory device disclosed in Japanese Patent Application Laid-open No. 63-166274, a control gate is formed by an N-type impurity region in a semiconductor layer, and a floating gate electrode is formed by a single-layer conductive layer such as a polysilicon layer (hereinafter may be called “single-layer-gate nonvolatile memory device”). Such a single-layer-gate nonvolatile memory device can be manufactured in the same manner as in a CMOS transistor process, since it is unnecessary to stack gate electrodes.